(1) Field of the Invention
The present invention relates to a method of driving a non-volatile flip-flop circuit using variable resistor elements, especially to a method of driving a non-volatile flip-flop circuit which can operate at high speed during normal operation and perform non-volatile operation when power is removed.
(2) Description of the Related Art
In recent years, the spread of portable devices has been driving the need for the miniaturization and reduced power consumption of semiconductor devices. The need for using nonvolatile memories for portable devices is also increasing. Non-volatile memories that are in practical use today include flash memories, ferroelectric random-access memories (FeRAMs), etc. In portable devices, a non-volatile memory is sometimes contained within a logic circuit to achieve miniaturization. Furthermore, semiconductor devices, mainly such as Silicon chips, for processing data are required not only miniaturization and reduced power consumption but also increased speed. However, flash memories, which are typical non-volatile memories, have slow writing operation and need a high voltage. Therefore, flash memories are not suitable for portable devices. Accordingly, FeRAMs, which can operate faster with lower power consumption, are attracting attention. However, mounting an FeRAM on a Silicon chip entails the problem of increased process costs because of the high temperature needed for forming ferroelectric films and the use of precious metals such as Pt, etc. as electrodes. In contrast, constructing a circuit by adding a non-volatile memory externally to a Silicon chip prevents the miniaturization and reduced weight of a device since it increases the area for mounting the circuit. In addition, the operation speed of a logic device comprising Silicon chips is higher that that of the above-mentioned non-volatile memory, and therefore the input/output time of data to/from the non-volatile memory creates overhead for the processing of the logic device.
Japanese Unexamined Patent Publication No. 2000-293989 suggests a circuit configuration which makes use of both the fast operation of Silicon devices and the non-volatility of non-volatile memories. This circuit has a configuration of a flip-flop (hereinafter referred to as FF) circuit, which is often used for Silicon devices, and additionally has ferroelectric capacitors. In normal operation, the circuit operates at a high speed as in a logical operation of a Silicon device, and when necessary, it writes data in the ferroelectric capacitors.
The operation of the circuit disclosed in the above-mentioned unexamined patent publication (see pages 6-9 and FIG. 2 of the publication) will be explained. FIG. 8 shows the circuit configuration of FIG. 2 in the publication. The circuit has an FF that comprises two inverters: one consists of transistors 101 and 102, and the other consists of transistors 103 and 104. The output terminal of the former inverter is connected to the input terminal of the latter inverter, and the output terminal of the latter inverter is connected to the input terminal of the former inverter. Two memory nodes 109 and 110 are connected to bit lines 111 and 112 via pass transistors 105 and 106, respectively, whose gates are connected to a word line 113. Ferroelectric capacitors 107 and 108 are connected between a plate (PL) line 115 and the memory nodes 109 and 110 respectively.
READ and WRITE operations perform in a similar manner to usual flip-flop circuits.
The operation to store data (hereinafter referred to as STORE operation) into the ferroelectric capacitors 107 and 108 is performed as follows: Firstly, the voltage of the plate line 115 which is usually set to half the supply voltage Vdd is increased to the supply voltage Vdd. Then, the voltage is changed to the ground voltage. By this operation, the voltages applied to the ferroelectric capacitors 107 and 108 become opposite to each other, according to the voltages Q1 and Q2 of the memory nodes 109 and 110, respectively. Secondly, the voltage of the plate line 115 is set to 0 V and the voltage DD of a power line 114 is set to 0 V to remove power. By these operations, the polarization directions of the ferroelectric capacitors 107 and 108 are set opposite to each other.
The operation to recall data (hereinafter referred to as RECALL operation) from the ferroelectric capacitors 107 and 108 is performed as follows: The voltage DD of the power line 114 is increased gradually, while the voltage of the plate line 115 is set to 0 V. The change of the polarization state of the ferroelectric capacitors 107 and 108 varies depending on the direction of polarization and the direction of the voltage applied. For this reason, when the supply voltage is increased, one ferroelectric capacitor causes a polarization reversal while the other ferroelectric capacitor does not. This creates a difference in the effective capacitances of one ferroelectric capacitor and the other ferroelectric capacitor. This results in a difference in the increasing rates of the voltages of the memory nodes 109 and 110 due to the rise of the supply voltage. By using this difference, the voltages Q1 and Q2 of the memory nodes 109 and 110 can be reset.
However, the above-mentioned prior art has the following problems:
The first problem is that a polarization of a ferroelectric substance reverses when an electric field applied thereto exceeds a certain value (coercive electric field). Data “0” and “1” are expressed by the state of this polarization. When an electric field lower than the coercive electric field is applied, slight polarization reversal also occurs. Accordingly, even when a voltage lower than the coercive electric field is applied to the ferroelectric substance in the operations other than STORE and RECALL operations, the polarization state changes slightly. This repetition of applying the lower voltage causes a phenomenon called “disturbance” which destroys a polarization state to be maintained. In order to prevent the disturbance of the ferroelectric capacitors 107 and 108, the voltage applied to the ferroelectric capacitors 107 and 108 must be controlled precisely.
The second problems is that the ferroelectric capacitors 107 and 108 are connected to the two memory nodes 109 and 110 of the FF circuit so that the parasitic capacitances of the memory nodes 109 and 110 increase. Also while the FF section is in operation, a voltage is applied to the ends of the path from the ferroelectric capacitor 107 to the ferroelectric capacitor 108 via the plate line 115. The values of the leakage current of the ferroelectric capacitors 107 and 108 are higher than those of the leakage current of an insulator layer used for Silicon devices such as SiO2. Therefore, a leakage current occurs in the above path while the FF circuit is in operation. In addition, during normal operation, a current that is necessary for holding the voltage of the plate line at Vdd/2 increases current consumption.